1. Field of the Invention
The present invention relates to a semiconductor device using a thin film transistor (TFT) provided on an insulating substrate such as a glass substrate, and a method for fabricating the same. In particular, the present invention relates to a semiconductor device which can be used for an active-matrix liquid crystal display apparatus and a method for fabricating the same.
2. Description of the Related Art
Active-matrix liquid crystal display apparatuses and image sensors using TFTs for driving their pixels are typical semiconductor apparatuses having TFTs formed on a glass substrate or other insulating substrate. Generally, the TFTs used in these apparatuses are formed from thin-film silicon semiconductors.
Such thin-film silicon semiconductors are roughly classified into two types: amorphous silicon (a-Si) semiconductors and crystalline silicon semiconductors.
Of these two types, the amorphous silicon semiconductor is preferred and enjoys general use because it has a low processing temperature and is easily manufactured using a vapor deposition method, thus lending itself to mass production. Compared to the crystalline silicon semiconductor, however, the amorphous silicon semiconductor is inferior in properties such as electrical conductivity. It is therefore strongly desired to establish an efficient fabrication method for TFTs formed from the crystalline silicon semiconductors to achieve faster response characteristics of the semiconductor devices fabricated from them.
The crystalline silicon semiconductors currently known include polycrystalline silicon, microcrystalline silicon, amorphous silicon containing crystalline components, semi-amorphous silicon having an intermediate state between crystalline and amorphous forms, etc. In general, each of the TFTs formed from these crystalline silicon semiconductors has a layered structure in which a substrate, an island-shaped semiconductor layer, a gate insulating film and a gate electrode traversing the island semiconductor layer are formed in this order (i.e., top gate type structure).
FIG. 18A is a plan view showing a conventional TFT made from the crystalline silicon semiconductor, and FIG. 18B is a cross-sectional view taken along a line 18B-18B' in FIG. 18A. FIGS. 19A through 19D are cross-sectional views showing a fabrication process of the TFT taken along the line 18B-18B' in FIG. 18A. FIGS. 20A through 20D are cross-sectional views showing the fabrication process of the TFT taken along a line 20A-20A' in FIG. 18A. This conventional TFT is fabricated as follows.
First, a film made of SiO.sub.2 or SiN.sub.x is deposited on an insulating substrate 1100, such as a glass substrate, to an appropriate thickness by sputtering or the like. A semiconductor silicon film is formed on the film to a thickness of about 100 nm by a CVD method or the like.
Subsequently, a thermal treatment process such as a heat treatment at about 600.degree. C. in a furnace or excimer laser irradiation is performed so as to crystallize the semiconductor silicon film. Thereafter, the semiconductor silicon film is patterned into a rectangular island shape. Alternatively, the patterning process can be conducted prior to the thermal treatment process. Specifically, the semiconductor silicon film is patterned into a rectangular island shape. Thereafter, the thermal treatment process such as a heat treatment at about 600.degree. C. in a furnace or excimer laser irradiation is performed so as to crystallize the island-shaped semiconductor silicon film. In this way, a crystalline semiconductor island 1101 shown in FIGS. 19A and 20A is obtained.
Next, as shown in FIGS. 19B and 20B, a gate insulating film 1102 is formed on the entire surface of the substrate 1100 by sputtering or a CVD method so as to cover the crystalline semiconductor island 1101. A thickness of the gate insulating film 1102 is about 100 nm. The gate insulating film 1102 is made of SiO.sub.2 or SiN.sub.x. Subsequently, a gate electrode 1103 is formed so as to traverse the rectangular crystalline semiconductor island 1101. The gate electrode 1103 is made of a conductive material.
Next, as shown in FIGS. 19C and FIG. 20C, a region of the crystalline silicon island 1101, on which the gate electrode 1103 is not formed, is doped with donor ions or acceptor ions using the gate electrode 1103 as a mask. This doping process can be conducted in the presence of the gate insulating film 1102 or after removing the region of the gate insulating film 1102 on which the gate electrode 1103 is not formed by etching. By doping part of the crystalline silicon island 1101 with donor ions or acceptor ions, source/drain regions 1106 are formed in the crystalline semiconductor island 1101.
Then, as shown in FIG. 20D, the source/drain regions 1106 of the crystalline semiconductor island 1101 are partially exposed. Subsequently, source/drain electrodes 1104 are formed so as to cover the exposed parts without being in contact with the gate electrode 1103, thereby completing the TFT. It has been reported in the recent result of the research that the thus fabricated TFT has a mobility of 100 cm.sup.2 /V.cndot.s or higher.
In order to apply TFTs to a liquid crystal display apparatus, there are two main problems to be solved: reduction in an OFF current across a TFT and improvement in reliability.
Due to its structure, the thus fabricated TFT has a disadvantage in that a thickness of part of the gate insulating film 1102 covering the side faces of edges of the crystalline semiconductor island 1101 is smaller than that on the upper surface of the crystalline semiconductor island 1101. This can be seen as a portion P marked with a double dashed line in FIG. 18B. Otherwise, the edges of the crystalline semiconductor island 1101 cannot be covered with the gate insulating film 1102.
The inventors of the present invention carried out an experiment using tetraethoxysilane (TEOS) which is recognized as having high step coverage performance. As a result, it was confirmed that a thickness of part of the gate insulating film covering the side faces of the edge of the crystalline semiconductor island is about 60% of that formed on the upper surface of the crystalline semiconductor island.
An electric field in the gate insulating film 1102 having a small thickness is higher than an average electric field in the gate insulating film 1102 positioned on the upper surface of the crystalline semiconductor island 1101. As a result, electric breakdown inevitably occurs in the regions having a little thickness. Furthermore, various problems such as failures and deterioration of performance in TFTs are caused by a phenomenon generally called "hot electron effect". This hot electron effect further induces other phenomena related to the electric field strength such as implantation of unnecessary electric charges into an insulator.
A measure to counter the deterioration of TFT characteristics resulting from a small thickness of part of the gate insulating film covering the side faces of the edges of the above-mentioned crystalline semiconductor island is proposed in Japanese Laid-Open Patent Publication No. 6-37317 and corresponding U.S. Pat. No. 5,130,264. In Japanese Laid-Open Patent Publication No. 6-37317, an insulating film is formed by oxidizing the periphery of a region serving as a TFT in the semiconductor silicon film after the semiconductor film is formed. As a result, the crystalline semiconductor island is formed so as to be buried in a silicon oxide wall to uniformize the thickness of the gate insulating film. In this way, the above-mentioned problem resulting from the small thickness of part of the gate insulating film is solved.
As a method for oxidizing the silicon film, high-temperature vapor oxidation at about 800.degree. C. and low-temperature plasma oxidation at about 600.degree. C. have been proposed. This high-temperature vapor oxidation method seems to be extremely effective in fabricating a crystalline silicon TFT in which a maximum temperature exceeding 800.degree. C. is used or in fabricating a single-crystalline silicon TFT. In view of application of TFTs to a liquid crystal display apparatus, it is necessary to use a glass substrate to achieve a large display size and reduction of the fabrication cost. However, the above-mentioned thermal oxidation process cannot be applied because of low heat-resistance of the glass substrate.
As a measure to counter this problem of heat-resistance, Japanese Laid-Open Patent Publication No. 6-37317 has proposed a plasma anodizing technique at a temperature in the range of 500.degree. C. to 600.degree. C. Generally, in a crystalline silicon film which is formed by a low-temperature process having the maximum temperature of about 600.degree. C., crystal grains having a diameter in the order of .mu.m or less are distributed. Each crystal grain has a twin structure in which crystals having various crystal orientations are distributed in a branch-like manner. A number of lattice defects are present in one crystal grain as well as in the boundary region of crystal grains.
As a method for examining the condition of the crystal growth of a crystalline silicon film, a method called secco etching is generally known. The secco etching utilizes the principle that silicon in the boundary regions of crystal grains is more rapidly oxidized and etched as compared with silicon in crystal grains if a surface of a crystalline silicon film is etched under the appropriate condition using an etchant having the oxidation function. By this method, the size of a crystal grain can be easily observed using an optical microscope.
As is apparent from this principle of secco etching, if an oxidation process is conducted on the crystalline silicon film as described in Japanese Laid-Open Patent Publication No.6-37317, unevenness occurs on the interface between the semiconductor silicon island and the SiO.sub.2 wall. The unevenness of the interface results in concentration of electric charges and reduction of the mobility of TFTs. In particular, the characteristics of TFT having a mobility of 100 cm.sup.2 /V.cndot.s or higher may be significantly deteriorated. Thus, the method described in Japanese Laid-Open Patent Publication No.6-37317 is not considered to be effective for mass production.
The inventors of the present invention examined an OFF current using a TFT having the structure shown in the conventional example. As a result, it became apparent that a width of a channel of TFT and the minimum value of an OFF current have a linear relationship, and thus an OFF current of about 1 to 2 pA flows even if a channel width is assumed to be zero according to the calculation. The reason why this phenomenon occurs is considered to be because a leakage current in the vicinity of the edges of the crystalline semiconductor island becomes larger than that in the other portion due to the concentration of the electric field in the vicinity of the edge of the crystalline semiconductor island. The TFTs cannot be applied to a liquid crystal display apparatus unless these problems are solved.